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Kilopass' Next-Generation Gusto-2 Targets Instant-On Mobile Devices

Kilopass Technology, Inc announced Gusto-2, its second generation of code storage products, to serve the increasing numbers of new system-on-chip (SoC) designs for instant-on mobile devices. The targeted SoCs perform functions, such as digital monitoring, near-field communications (NFC), and other applications serving the emerging market of Internet of things. Gusto-2 provides the low power, large storage capacity, and performance these SoCs demand for execute-in-place in a silicon footprint equivalent to that of the shadow SRAM required to operate the external serial EEPROM or Flash being displaced.
Gusto-2 Antifuse NVM affords the low static power operation that SRAM cannot, while enabling field re-programmability that ROM cannot. First Gusto-2 products will be available in capacities of 256kb, 512kb, and 1024kb. And Gusto-2's wide synchronous Open Core Protocol (OCP) interface will enable easy connection to all modern embedded processor buses. Gusto-2 antifuse NVM IP is initially available on 55nm and 65nm process nodes with additional nodes forthcoming.
New SoC designs in this category will come with Bluetooth, Zigbee, and WiFi peripheral circuits for such applications as sophisticated designs for home automation, security, healthcare monitoring, and financial transactions. The typical size of an embedded program to serve these applications ranges from 32 to 128 kbytes.
SoC designs employ an embedded SRAM and external Serial EEPROM/Flash NVM in two instances. First, the combination is used at small process geometries where on-chip EEPROM/Flash is unavailable. Second, it is used where the amount of external NVM is too small to warrant the extra cost of adding it to a standard logic process. Replacing this combination with Gusto-2 saves the SoC design I/O pads ring pins. It also reduces the system manufacturer bill-of-materials by one component and saves logistics and inventory cost.
Pricing and Availability Gusto-2 is available for 2013 Q1 SoC designs. It will initially be enabled on the 55nm and 65nm logic processes at IDMs and mainstream pure play foundries with enablement on smaller process nodes following

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